The present invention relates to computer system bus architecture.
The implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like have provided major advances in the performance of personal computers (both workstation and network servers). These sophisticated peripheral devices have vastly increased data transfer rates. The peripheral devices""data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the xe2x80x9cPeripheral Component Interconnectxe2x80x9d or xe2x80x9cPCIxe2x80x9d A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.2; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; and PCI BIOS Specification, revision 2.1, the disclosures of which are hereby incorporated by reference. These PCI specifications are available from the PCI Special Interest Group, 2575 N. E. Kathryn #17, Hillsboro, Oreg. 97214.
The PCI bus is a mezzanine bus between the host or local bus in the computer, to which are connected the processor, memory, and the I/O bus, such as ISA or EISA. The bus was designed to have a high throughput and to take advantage of the increasing number of local processors that support I/O functions. For example, most disk controllers, particularly SCSI controllers, and network interface cards (NICs) include a local processor to relieve demands on the host processor. Similarly, video graphics boards often include intelligent graphics accelerators to allow higher level function transfer. Typically these devices have the capability of operating as bus masters, to allow them to transfer data at the highest possible rates.
Because of the number of potential devices trying to be bus masters, an arbitration scheme is required. A common arbitration scheme is least-recently-used (LRU). In certain cases, such as described in U.S. Pat. No. 5,535,395, entitled xe2x80x9cPrioritization of Microprocessors in Multiprocessor Computer Systems,xe2x80x9d which is hereby incorporated by reference, the LRU scheme is modified so that the LRU of just the various requesters is used.
One of the types of devices that may be connected to the PCI bus is a Universal Serial Bus (USB) host controller. USB is a cable bus that supports data exchange between a host computer (USB host) and a wide range of simultaneously accessible peripherals (USB devices). USB supports a maximum data rate of 12 megabits/second.
The USB host controller provides access to the USB devices in the system. The host controller performs several duties with regard to the USB and its attached USB devices. These duties include reporting and managing the states of the USB devices, converting protocol and data information between a native format and a bit stream transmitted on the USB, frame generation, processing requests for data transmission, and transmission error handling.
USB allows up to 127 devices to run simultaneously on a computer, with peripherals such as monitors and keyboards acting as additional plug-in sites, or hubs. The USB physical interconnect is a tiered star topology. A hub is at the center of each star, and acts as a concentrator. A hub has a single upstream port in communication with the host controller and a plurality of downstream ports. Each downstream port allows connection to another hub or a function (device). Each wire segment is a point-to-point connection between the USB host and a hub or a USB device, or a hub connected to another hub or USB device. Conventional USB systems permit only a single host capable of communicating with the PCI bus at a rate of 12 megabits/second. When a hub is connected to the USB port, the available 12 megabits/second bandwidth is divided among the downstream ports. Thus, if a single hub having four downstream ports is used, the four downstream ports would each only provide an average of three megabits/second or less.
The present invention is a method and apparatus for controlling access to a bus. A plurality of requests for the bus are received from a plurality of requesters. A respective record is stored in a FIFO queue corresponding to each of the requestors. A next one of the records is read from the FIFO queue. Bus access is granted to the one of the requestors identified in the next record.
Another aspect of the invention is a method and apparatus for controlling access to a PCI bus. An arbiter arbitrates multiple requests for a PCI bus. Each request is initiated by a respective communication from a respective one of a plurality of USB ports. Full-rate USB data transfer capability is provided between the PCI bus and the plurality of USB ports.
Still another aspect of the invention is a breakout box. The breakout box includes a housing having a plurality of USB ports connected thereto, and a plurality of cables. Each of the plurality of cables is connected at a first end to a respective one of the USB ports. Each of the plurality of cables has a second end remote and separately positionable from the housing. The second end of each of the plurality of cables has a respective USB terminal connected thereto. Each of the plurality of cables provides full-rate USB data transfer capability.